1. Field of the Invention
The present invention relates to improved area efficient memory architecture with decoder self test and debug capability. More particularly, it relates to providing an integrated test architecture/methodology within the memory for high-speed address decoder testing and high speed memory operation.
2. Description of the Related Art
Over the years, semiconductor devices have become considerably smaller and faster. The semiconductor technology trends have consistently followed Moore's Law as the technology has shrunk by a factor of 1.5 every year. The miniaturization of devices has also resulted in increased complexity and consequently higher clock speeds for integrated circuits. For instance, complex application specific integrated circuits (ASICs) today have several million transistors on a single chip. Since these chips can hold more transistors, a single chip has more logic blocks. As a result, on-chip memories have become extremely popular for fast memory access in System on Chip (SoC) devices. Each memory block takes up significant silicon area and as a result, most of the silicon area on ASICs is dedicated to these embedded memories. As ASIC designs become more memory dominated, the probability of memory errors has increased due to manufacturing faults and process variations. Hence, Design for Test (DFT) and test reliability are very important aspects in the ASIC design process.
The testing is done using on-chip test devices called Built in Self Test (BIST) devices. These BISTs perform failure testing on the memories at very high clock speeds. This is a major bottleneck for the development of reliable high-speed ASICs as most of the current BIST architectures do not provide reliable memory testing at high clock speeds. The few current BIST devices that do provide reliable testing are very inefficient in terms of operation speed.
Today's embedded memories are full custom volatile random access memories (RAMs) that are designed and optimized for high speed, low power and small area. These memories are categorized by their operation mode as synchronous or asynchronous memories. While the synchronous memories perform operations on the edges of the input clock, the operations inside the asynchronous memories are independent of the input clock. The memories are also categorized by their storage means and detection techniques into static or dynamic RAMs (SRAMs/DRAMs). DRAMs occupy less silicon area but the storage elements in DRAMs have to be refreshed at regular intervals. SRAMs are larger memories that do not require regular refreshes and as a result, they have faster access times and are ideal for high speed ASICs. The present invention is discussed in relation to synchronous memories, but the same fundamentals can also be applied to the asynchronous memories as well.
FIG. 1 illustrates the structure of a known single port embedded memory 10. The memory contains a data input port (DATA INPUT), an address port (ADDRESS), a memory select port (CSN), an output enable port (OEN), an external clock port (CLOCK), a write enable port (WEN), and an output port (DATA OUTPUT) or a subset of these I/O ports. The structure has an address decoder 12, a control/clock generator 14, a memory core 16, and I/O port blocks 18. Similarly, a dual port memory structure contains two decoders (X and Y decoders), a control/clock generation circuitry, a memory core, I/O port blocks, and several dummy paths. All mentioned blocks are made in form of leaf cells and are abutted to form a memory block of desired word×bit configuration. Hence, full memory design process involves designing all the leaf cells in a new technology and altering the design parameters for interaction between leaf cells for proper memory functioning.
Correct operation of the address decoder and all other leaf cells is very important for proper functioning of the memory. A normal address decoder in a memory contains latches to store the addresses. These addresses are statically decoded and the valid decoded value is clocked to select a row or column (or both) in the memory core to write onto or read from the memory cells. In dynamic decoders the row select signal called the wordline is subjected to a precharge mechanism using an internally generated memory clock. The decoder outputs or the word lines are then used to select the memory cell enable pins. Manufacturing defects in the address decoder can result in faults like stuck-at on the word lines, wrong selection and multiple word line selections. These faults arise when the setup or hold time requirements for decoder latches are not met or there are some other timing problems with the block.
U.S. Pat. No. 6,470,475 relates to a synthesizable synchronous static random access memory that comprises custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high-speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs. The limitation of the aforementioned patent document is that it does not suggest high speed and minimal clock cycle testing of the memory address decoder.
In prior art, a Built in Self Test (BIST) device performs fault testing for all leaf cells in a memory and generates results for memory as a block. The most common way to detect the address decoder faults is to use some standard march algorithms which contain special march elements in a specified order. These algorithms have several disadvantages as they are highly unreliable in detecting the address decoder faults. As mentioned in book ‘Testing Semiconductor Memories: Theory And Practice’ by A. J. Vande Goor, the disadvantages of current memory testing devices and more specifically decoder testing are as follows:
The tests take about four operations per word to detect the address decoder faults. Hence, the test time for memory address decoder is very large if the memory size is big.
Some other kinds of faults like coupling faults or IO faults may mask the address decoder faults as the fault is detected through the memory output port.
There is no way of viewing the address decoder faults as the paths come out through the memory core.
Debugging the address decoder faults is very hard as segregating the decoder faults from other faults is not possible.